Usman Siddique

An inquisitive Computer Engineer with a passion for developing innovative and novel computing technologies catered towards the semiconductor industry. Dedicated , and enthusiastic, and thorough engineer with experience in conducting projects and meeting deadlines. An articulate and confident presenter capable of explaining complex topics in simplified terms to all audiences. Committed team member with strong problem-solving, managerial and organizational skills acquired through professional and academic experience and collaborative voluntary work. Capable of organizing events at different scales for a variety of audiences. Proficient in a considerable number of tools and technologies associated with the semiconductor industry.

• Digital Design
• FPGAs
• MicroControllers and MicroProcessors
• Embedded Systems

Work Experience

• Lab Technician: NCT Group, ZITI, Heidelberg University, Germany Oct 2023 — Present

  • Working at the Novel Computing Technologies Group (NCT) at the Institute of Computer Engineering (ZITI).

• Research Intern: SMR 3891 - School on SoC Based FPGAs, ICTP, Trieste, Italy Nov 2023

  • Participated in the two-week joint ICTP-IAEA School on Systems-on-Chip Based on FPGA for Scientific Instrumentation and Reconfigurable Computing (SMR 3891) focusing on FPGA-based SoCs and their applications within scientific instrumentation and reconfigurable computing, with a specific emphasis on nuclear and particle physics experiments.
  • Acquired hands-on expertise in SoC architecture, hardware/software interface, VHDL for FPGA design, and embedded C.
  • Successfully completed a project involving the development of embedded instruments for nuclear applications and particle physics experiments.
  • Gained proficiency in real-time data acquisition, detector signal processing, and event reconstruction.
  • Explored FPGA's role in accelerating AI algorithms and its application in high-performance computing architectures.
  • Engaged in tutorials and activities, fostering familiarity with professional software design tools and hardware platforms.

• Embedded Software Engineer: RapidSilicon, Lahore, Pakistan Feb 2023 — Aug 2023

  • Designed a testing infrastructure in python using pytest to automate SoC prototype test cases making regression and testing much more straightforward.
  • Setup and ran various testcases for BootROM, flash, SRAM and other IPs for multiple versions of the SoC prototype on an FPGA.
  • Underwent basic training and learned various on how to write embedded software.

• Contributor: OpenTCAM, Google Summer of Code Jun 2022 — Nov 2022

  • Development of a Python compiler for a resource efficient SRAM based TCAM memory.

• Associate Design Verification Engineer: RapidSilicon, Lahore, Pakistan Dec 2021 — Jan 2023

  • Developed the GPIO PADs and GPIO Controller Verification IP
  • Developed from scratch to verify GPIO functionality and IO-Muxing.
  • Worked on the integration and development of a GPIO PADs VIP of an FPGA-based SoC.
  • Completed code and functional coverage closure.
  • Additional Tasks
  • Wrote Python script to generate exclusion reports and files using coverage reports.
  • Did regression reporting and coverage status for various IP blocks.
  • Wrote exclusion file for GPIO and QSPI IP blocks.
  • Designed a SystemVerilog UVM environment
  • At the unit level for a GPIO PAD IP.
  • Training
  • Hands-on training of "SystemVerilog Accelerated Verification with UVM" from Cadence training.
  • Hands-on training of "SystemVerilog for Design and Verification" from Cadence training.

• Associate Design Verification Engineer: Lampro Mellon, Lahore, Pakistan Oct 2020 — Nov 2021

  • Onboarding of APB UART IP and Verification IP (VIP) with Block-PIO-SiFive
  • Hands-on training of FOSS IP onboarding tools provided by SiFive.
  • Flow flush of Block-Pio-SiFive pre-onboarded flow.
  • Writing a test plan for the APB UART IP functionality testing.
  • Creating and simulating C tests for onboarded in-house UART.
  • Generate coverage using loopback verification IP (VIP) via C tests.
  • Linting and Clock Domain Crossing (CDC)
  • Hands-on learning of STA, Linting, and Clock Domain Crossing (CDC).
  • Understanding simulation flow of Synopsys SpyGlass.
  • Static verification including linting and Clock Domain Crossing (CDC) checks of:
  • in-house FIFOs
  • in-house UART
  • in-house UART integrated into RocketChip SoC
  • Designed a verification plan for all possible test case scenarios for an I2S IP.
  • IP Onboarding Automation:
    • Designed a Python-based parser for reading the XML file specifications of various IPs including clocks, resets, ports, bus-interface/s, interrupt/s, memory map; update their value and generate an updated XML and JSON configs.
    • The parser can also be used to generate a top wrapper for any IP in Verilog and SystemVerilog.

• SoC Trainee Engineer: Lampro Mellon, Lahore, Pakistan Jan 2020 — Oct 2020

  • Received a 100% scholarship for the Lampro Mellon Michanikos program.
  • Learned various concepts overt the training such as:
    • Verilog
    • System Verilog
    • Layered test benches using System Verilog
    • Familiarity with RISC-V ISA
  • Worked on various projects including:
    • Design of an 8-bit 10x10 matrix multiplier via an FSMD approach in SystemVerilog using Vedic multiplication.
    • Design of a single cycle RISC-V processor in Verilog.
    • Design of a 5-stage RISC-V processor in System Verilog.
    • Design of a layered testbench for the verification of the AHB-Lite Master module.
    • Verification of SweRV-EH1 core using Google DV and RISC-V environment.
    • Design of AMBA based AHB to APB bridge.

• Embedded Design Engineer: Anzen Pvt Ltd, Islamabad, Pakistan Aug 2019 — Dec 2019

  • Worked on the design and development of IoT based products for the consumer market including:
    • Designed a 3-switch module that can be fitted in a wall socket and can be used to control a total of 3 AC lights or fans.
    • Improved upon an existing design of a single switch module for high-powered loads e.g., Air conditioner.
    • Worked on design and development of a smart geyser thermostat module that can control a geyser via mobile app and indoor control unit.

• Embedded Systems Engineer (Internee): AKSA-SDS, Islamabad, Pakistan May 2019 — July 2019

  • Learned and implemented various concepts including:
    • Used Arduino and Nextion TFT Touch panels to design an interactive heads-up display.
    • Learned how to use Altium Designer and implemented design and PCB changes in various schematics.
    • Designed an IO shield for the ESP32 MCU using Altium Designer.

Education

• B.Sc.: National Univeristy of Computer and Emerging Sciences (FAST-NUCES) 2014–2018

Projects

• OpenTCAM: Google Summer of Code 2022 Jun 2022 — Nov 2022

  • OpenTCAM is an open-source Python framework that can be used to create the design and layouts of a customizable SRAM-based TCAM memory to use in FPGA and ASIC designs.

• EMG based Below the Elbow Prosthetic Arm: BS Thesis Jan 2018 — Dec 2018

  • This project investigates the design of a prosthetic arm to mimic its human counterpart. It examines acquiring data signals from the upper arm, creating a CAD model of the arm which can be 3D printed.

• UVM Teshbench for an ALU: GitHub

  • This project outlines the design and implementation of a SystemVerilog UVM based testbench for an 8-bit ALU.

• Prototyping Board for the AVR ATMega32A:

  • This project examines the design of an Arduino UNO based prototyping board for the AVR ATMega32A Microcontroller using Altium Designer.

• Trigonometric Double Float Point Calculator: GitHub

  • This project examines the design and implementation in Verilog of a Trigonometric functions calculator with IEEE 745 double float point precision format.

• Matrix Multiplier: GitHub

  • This project outlines the design and implementation of an 8-bit 10x10 matrix multiplier using Vedic multiplication. It takes two matrices i.e. matrix A and matrix B and gives their product matrix C i.e. C=A*B.